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| Agilent HCPL-260L/ 060L/263L/063L High Speed LVTTL Compatible 3.3 Volt Optocouplers Data Sheet Features * Low power consumption * 15 kV/s minimum Common Mode Rejection (CMR) at VCM = 50 V * High speed: 15 MBd typical * LVTTL/LVCMOS compatible Description The HCPL-260L/060L/263L/063L are optically coupled gates that combine a GaAsP light emitting diode and an integrated high gain photo detector. An enable input allows the detector to be strobed. The output of the detector IC is an open collector Schottky-clamped transistor. The internal shield provides a guaranteed common mode transient immunity specification of 15 kV/ s. Functional Diagram HCPL-260L/060L NC ANODE CATHODE NC 1 2 3 4 SHIELD 8 7 6 5 VCC VE VO GND ANODE 1 CATHODE 1 CATHODE 2 ANODE 2 1 2 3 4 SHIELD HCPL-263L/063L 8 7 6 5 VCC VO1 VO2 GND * Low input current capability: 5 mA This unique design provides maximum AC and DC circuit isolation while achieving LVTTL/LVCMOS compatibility. The optocoupler AC and DC operational parameters are guaranteed from -40C to +85C allowing trouble-free system performance. * Guaranteed AC and DC performance over temperature: -40C to +85C * Available in 8-pin DIP, SOIC-8 * Strobable output (single channel products only) * Safety approvals; UL, CSA, VDE (pending) Applications * Isolated line receiver * Computer-peripheral interfaces * Microprocessor system interfaces * Digital isolation for A/D, D/A conversion * Switching power supply * Instrument input/output isolation * Ground loop elimination * Pulse transformer replacement * Field buses TRUTH TABLE (POSITIVE LOGIC) LED ON OFF ON OFF ON OFF ENABLE H H L L NC NC OUTPUT L H H H L H TRUTH TABLE (POSITIVE LOGIC) LED ON OFF OUTPUT L H A 0.1 F bypass capacitor must be connected between pins 5 and 8. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. These optocouplers are suitable for high speed logic interfacing, input/output buffering, as line receivers in environments that conventional line receivers cannot tolerate and are recommended for use in extremely high ground or induced noise environments. These optocouplers are available in an 8-pin DIP and industry standard SO-8 package. The part numbers are as follows: 8-pin DIP HCPL-260L HCPL-263L SO-8 Package HCPL-060L HCPL-063L Ordering Information Specify Part Number followed by Option Number (if desired). Example: HCPL-260L #XXX 060 = VDE 0884 VIORM = 630 Vpeak Option 500 = Tape and Reel Packaging Option Option data sheets available. Contact Agilent sales representative or authorized distributor for information. Schematic HCPL-260L/060L ICC 8 IO 6 VCC 1 IF1 HCPL-263L/063L ICC 8 IO1 7 VCC VO1 IF 2+ VO + VF1 VF - 3 SHIELD IE 5 7 VE GND - 2 SHIELD 3 - IF2 IO2 6 VO2 USE OF A 0.1 F BYPASS CAPACITOR CONNECTED BETWEEN PINS 5 AND 8 IS RECOMMENDED (SEE NOTE 5). VF2 + 4 SHIELD 5 GND Package Outline Drawings 8-Pin DIP Package 7.62 0.25 (0.300 0.010) 5 6.35 0.25 (0.250 0.010) 9.65 0.25 (0.380 0.010) TYPE NUMBER 8 7 6 OPTION CODE* DATE CODE A XXXXZ YYWW RU 1 1.19 (0.047) MAX. 2 3 4 UL RECOGNITION 1.78 (0.070) MAX. + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002) 5 TYP. 4.70 (0.185) MAX. 0.51 (0.020) MIN. 2.92 (0.115) MIN. 1.080 0.320 (0.043 0.013) 0.65 (0.025) MAX. 2.54 0.25 (0.100 0.010) DIMENSIONS IN MILLIMETERS AND (INCHES). *MARKING CODE LETTER FOR OPTION NUMBERS "L" = OPTION 020 "V" = OPTION 060 OPTION NUMBERS 300 AND 500 NOT MARKED. Small Outline SO-8 Package 8 7 6 5 3.937 0.127 (0.155 0.005) PIN ONE 1 0.406 0.076 (0.016 0.003) 2 XXX YWW 5.994 0.203 (0.236 0.008) TYPE NUMBER (LAST 3 DIGITS) DATE CODE 3 4 1.270 BSG (0.050) * 5.080 0.127 (0.200 0.005) 7 0.432 (0.017) 45 X 3.175 0.127 (0.125 0.005) 0 ~ 7 1.524 (0.060) 0.203 0.102 (0.008 0.004) 0.228 0.025 (0.009 0.001) * TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH) 5.207 0.254 (0.205 0.010) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX. 0.305 MIN. (0.012) Solder Reflow Temperature Profile (Surface Mount Option Parts) 260 240 220 200 180 160 140 120 100 80 60 40 20 0 0 Regulatory Information The HCPL-260L/060L/263L/063L are pending by the following organizations: T = 145C, 1C/SEC T = 115C, 0.3C/SEC UL TEMPERATURE - C Approval (pending) under UL 1577, Component Recognition Program, File E55361. T = 100C, 1.5C/SEC CSA 1 2 3 4 5 6 7 8 9 10 11 12 Approval (pending) under CSA Component Acceptance Notice #5, File CA 88324. VDE TIME - MINUTES NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS HIGHLY RECOMMENDED. Approval (pending) according to VDE 0884/06.92. Insulation and Safety Related Specifications 8-Pin DIP (300 Mil) Value 7.1 7.4 0.08 SO-8 Value 4.9 4.8 0.08 Parameter Minimum External Air Gap (External Clearance) Minimum External Tracking (External Creepage) Minimum Internal Plastic Gap (Internal Clearance) Symbol L (101) L (102) Units mm mm mm Minimum Internal Tracking (Internal Creepage) Tracking Resistance (Comparative Tracking Index) Isolation Group NA CTI 200 NA 200 mm Volts Conditions Measured from input terminals to output terminals, shortest distance through air. Measured from input terminals to output terminals, shortest distance path along body. Through insulation distance, conductor to conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity. Measured from input terminals to output terminals, along internal cavity. DIN IEC 112/VDE 0303 Part 1 IIIa IIIa Material Group (DIN VDE 0110, 1/89, Table 1) VDE 0884 Insulation Related Characteristics Description Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage 300 V rms for rated mains voltage 450 V rms Climatic Classification Pollution Degree (DIN VDE 0110/1.89) Maximum Working Insulation Voltage Input to Output Test Voltage, Method b* VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial Discharge < 5 pC Input to Output Test Voltage, Method a* VIORM x 1.5 = VPR, Type and Sample Test, tm = 60 sec, Partial Discharge < 5 pC Highest Allowable Overvoltage* (Transient Overvoltage, tini = 10 sec) Safety Limiting Values (Maximum values allowed in the event of a failure, also see Figure 16, Thermal Derating curve.) Case Temperature Input Current Output Power Insulation Resistance at TS, V IO = 500 V Symbol Characteristic I-IV I-III 55/85/21 2 630 1181 Units VIORM VPR Vpeak Vpeak VPR VIOTM 945 6000 Vpeak Vpeak TS IS,INPUT PS,OUTPUT RS 175 230 600 109 C mA mW *Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section (VDE 0884), for a detailed description. Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. Absolute Maximum Ratings (No Derating Required up to 85C) Parameter Storage Temperature Operating Temperature Average Forward Input Current Symbol TS TA IF Package** Min. -55 -40 Max. 125 85 20 15 5 3 40 7 VCC + 0.5 5 50 7 85 60 260C for 10 sec., 1.6 mm below seating plane 260C for 10 sec., up to seating plane See Package Outline Drawings section V mW V V mA mA V mW Units C C mA Note Reverse Input Voltage Input Power Dissipation Supply Voltage (1 Minute Maximum) Enable Input Voltage (Not to Exceed VCC by more than 500 mV) Enable Input Current Output Collector Current Output Collector Voltage Output Collector Power Dissipation VR PI VCC VE IE IO VO PO Single 8-Pin DIP Single SO-8 Dual 8-Pin DIP Dual SO-8 8-Pin DIP, SO-8 2 1, 3 1 Single 8-Pin DIP Single SO-8 1 1 Lead Solder Temperature (Through Hole Parts Only) TLS Single 8-Pin DIP Single SO-8 Dual 8-Pin DIP Dual SO-8 8-Pin DIP 1, 4 Solder Reflow Temperature Profile (Surface Mount Parts Only) SO-8 **Ratings apply to all devices except otherwise noted in the Package column. Recommended Operating Conditions Parameter Input Current, Low Level Input Current, High Level[1] Power Supply Voltage Low Level Enable Voltage High Level Enable Voltage Operating Temperature Fan Out (at RL = 1 k )[1] Output Pull-up Resistor Symbol IFL* IFH** VCC VEL VEH TA N RL Min. 0 5 2.7 0 2.0 -40 330 Max. 250 15 3.3 0.8 VCC 85 5 4k Units A mA V V V C TTL Loads *The off condition can also be guaranteed by ensuring that VFL 0.8 volts. **The initial switching threshold is 5 mA or less. It is recommended that 6.3 mA to 10 mA be used for best performance and to permit at least a 20% LED degradation guardband. Electrical Specifications Over Recommended Temperature (T A = -40C to +85C) unless otherwise specified. All Typicals at V CC = 3.3 V, TA = 25C. All enable test conditions apply to single channel products only. See Note 5. Parameter High Level Output Current Input Threshold Current Sym. IOH* ITH Min. Typ. 4.5 3.0 Max. 50 5.0 Units A mA Test Conditions V CC = 3.3 V, V E = 2.0 V, VO = 3.3 V, IF = 250 A VCC = 3.3 V, V E = 2.0 V, VO = 0.6 V, IOL (Sinking) = 13 mA VCC = 3.3 V, V E = 2.0 V, IF = 5 mA, IOL (Sinking) = 13 mA VE = 0.5 V VCC = 3.3 V IF = 0 mA VE = 0.5 V VCC = 3.3 V IF = 10 mA VCC = 3.3 V, V E = 2.0 V VCC = 3.3 V, V E = 0.5 V Fig. 1 2 Note 1, 15 15 Low Level Output Voltage VOL* 0.35 0.6 V 3 15 High Level Supply Current Low Level Supply Current High Level Enable Current Low Level Enable Current High Level Enable Voltage Low Level Enable Voltage Input Forward Voltage Input Reverse Breakdown Voltage Input Diode Temperature Coefficient Input Capacitance ICCH ICCL IEH IEL* VEH VEL VF BVR* V F/ T A CIN 4.7 7.0 -0.5 -0.5 2.0 1.4 5 1.5 7.0 10.0 -1.2 -1.2 0.8 1.75* mA mA mA mA V V V V mVC 15 TA = 25C IF = 10 mA IR = 10 A IF = 10 mA 5 1 1 1 -1.6 -1.9 60 pF f = 1 MHz, VF = 0 V 1 *The JEDEC Registration specifies 0C to +70C. Agilent specifies -40C to +85C. Switching Specifications Over Recommended Temperature (T A = -40C to +85C), VCC = 3.3 V, I F = 7.5 mA unless otherwise specified. All Typicals at TA = 25C, V CC = 3.3 V. Parameter Propagation Delay Time to High Output Level Propagation Delay Time to Low Output Level Pulse Width Distortion Propagation Delay Skew Output Rise Time (10-90%) Output Fall Time (90-10%) Propagation Delay Time of Enable from VEH tp VEL Propagation Delay Time of Enable from VEL to VEH Sym. tPLH Package** Min. Typ. Max. Units 90 ns Test Conditions TA = 25C RL = 350 CL = 15 pF Fig. Note 6, 7, 8 1, 6, 15 tPHL 75 ns 1, 7, 15 |tPHL - tPLH| 8-Pin DIP SO-8 tPSK tr tf tELH 45 20 45 25 40 ns ns ns ns ns RL = 350 , CL = 15 pF, VEL = 0 V, V EH = 3 V 8 9, 15 8, 9, 15 1, 15 1, 15 9 10 tEHL 30 ns 11 *JEDEC registered data for the 6N137. **Ratings apply to all devices except otherwise noted in the Package column. Parameter Logic High Common Mode Transient Immunity Logic Low Common Mode Transient Immunity Sym. |CMH| |CML| Device Min. Typ. Units Test Conditions HCPL-263L 15,000 25,000 V/s |VCM | = 10 V VCC = 3.3 V, I F = 0 mA, HCPL-063L VO(MIN) = 2 V, RL = 350 , TA = 25C HCPL-260L 15,000 25,000 |VCM | = 50 V HCPL-060L HCPL-263L 15,000 25,000 V/s |VCM | = 10 V VCC = 3.3 V, I F = 7.5 mA, HCPL-063L VO(MAX) = 0.8 V, RL = 350 , TA = 25C |VCM| = 50 V HCPL-260L 15,00 25,000 HCPL-060L Fig. 11 Note 12, 14, 15 11 13, 14, 15 Package Characteristics All Typicals at T A = 25C. Parameter Sym. Package Input-Output I I-O* Single 8-Pin DIP Insulation Single SO-8 Input-Output VISO 8-Pin DIP, SO-8 Momentary Withstand Voltage** Input-Output RI-O 8-Pin, SO-8 Resistance Input-Output CI-O 8-Pin DIP, SO-8 Capacitance Input-Input II-I Dual Channel Insulation Leakage Current Resistance RI-I Dual Channel (Input-Input) Capacitance CI-I Dual 8-Pin Dip (Input-Input) Dual SO-8 Min. Typ. Max 1 Units A V rms 2500 Test Conditions Fig. Note 45% RH, t = 5 s, 16, 17 VI-O = 3 kV DC, TA = 25C RH 50%, t = 1 min, 16, 17 TA = 25C 1012 0.6 0.005 pF A VI-O =500 V dc f = 1 MHz, TA = 25C RH 45%, t = 5 s, VI-I = 500 V 1, 16, 19 1, 16, 19 20 1011 0.03 0.25 pG f = 1 MHz 20 20 *The JEDEC Registration specifies 0C to +70C. Agilent specifies -40C to +85C. **The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable), your equipment level safety specification or Agilent Application Note 1074 entitled "Optocoupler Input-Output Endurance Voltage." Notes: 1. Each channel. 2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not exceed 20 mA. 3. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not exceed 15 mA. 4. Derate linearly above +80C free-air temperature at a rate of 2.7 mW/C for the SOIC-8 package. 5. Bypassing of the power supply line is required, with a 0.1 F ceramic disc capacitor adjacent to each optocoupler as illustrated in Figure 11. Total lead length between both ends of the capacitor and the isolator pins should not exceed 20 mm. 6. The tPLH propagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge of the output pulse. 7. The tPHL propagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge of the output pulse. 8. t PSK is equal to the worst case difference in t PHL and/or tPLH that will be seen between units at any given temperature and specified test conditions. 9. See test circuit for measurement details. 10. The tELH enable propagation delay is measured from the 1.5 V point on the falling edge of the enable input pulse to the 1.5 V point on the rising edge of the output pulse. 11. The tELH enable propagation delay is measured from the 1.5 V point on the rising edge of the enable input pulse to the 1.5 V point on the falling edge of the output pulse. 12. CM H is the maximum tolerable rate of rise on the common mode voltage to assure that the output will remain in a high logic state (i.e., V o > 2.0 V). 13. CM L is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., V o < 0.8 V). 14. For sinusoidal voltages, (|dVCM | / dt)max = fCMVCM (p-p). 15. No external pull up is required for a high logic state on the enable input. If the VE pin is not used, tying VE to VCC will result in improved CMR performance. For single channel products only. See application information provided. 16. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together. 17. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage 3000 V rms for one second (leakage detection current limit, II-O 5 A). This test is performed before the 100% production test for partial discharge (Method b) shown in the VDE 0884 Insulation Characteristics Table, if applicable. 18. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage 6000 V rms for one second (leakage detection current limit, II-O 5 A). This test is performed before the 100% production test for partial discharge (Method b) shown in the VDE 0884 Insulation Characteristics Table, if applicable. 19. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together. For dual channel products only. 20. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. For dual channel products only. IOH - HIGH LEVEL OUTPUT CURRENT - A ITH - INPUT THRESHOLD CURRENT - mA 15 VCC = 3.3 V VO = 3.3 V VE = 2.0 V* IF = 250 A 10 * FOR SINGLE CHANNEL PRODUCTS ONLY 12 10 8 VOL - LOW LEVEL OUTPUT VOLTAGE - V 8-PIN DIP, SO-8 VCC = 3.3 V VO = 0.6 V 8-PIN DIP, SO-8 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -60 -40 -20 0 20 40 60 80 100 IO = 13 mA VCC = 3.3 V VE = 2.0 V* IF = 5.0 mA * FOR SINGLE CHANNEL PRODUCTS ONLY RL = 350 6 4 2 RL = 4 K 0 -60 -40 -20 0 20 40 60 80 100 RL = 1 K 5 0 -60 -40 -20 0 20 40 60 80 100 TA - TEMPERATURE - C TA - TEMPERATURE - C TA - TEMPERATURE - C Figure 1. Typical high level output current vs. temperature. Figure 2. Typical input threshold current vs. temperature. Figure 3. Typical low level output voltage vs. temperature. IOL - LOW LEVEL OUTPUT CURRENT - mA 70 IF - FORWARD CURRENT - mA 1000 8-PIN DIP, SO-8 TA = 25 C VCC = 3.3 V VE = 2.0 V* VOL = 0.6 V 60 * FOR SINGLE CHANNEL PRODUCTS ONLY 100 10 1.0 0.1 0.01 IF + VF - 50 IF = 5.0 mA 40 20 -60 -40 -20 0 20 40 60 80 100 0.001 1.1 1.2 1.3 1.4 1.5 1.6 TA - TEMPERATURE - C VF - FORWARD VOLTAGE - V Figure 4. Typical low level output current vs. temperature. Figure 5. Typical input diode forward characteristic. SINGLE CHANNEL PULSE GEN. ZO = 50 t f = t r = 5 ns IF 1 2 INPUT MONITORING NODE RM 3 4 VCC 8 7 6 PULSE GEN. ZO = 50 tf = tr = 5 ns 3.3 V IF INPUT MONITORING NODE OUTPUT V O MONITORING NODE 1 2 3 RM 4 DUAL CHANNEL VCC 8 3.3 V 0.1 F BYPASS RL 7 6 5 0.1 F BYPASS CL* GND RL OUTPUT V O MONITORING NODE *CL GND 5 *CL IS APPROXIMATELY 15 pF WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE. IF = 7.50 mA IF = 3.75 mA tPHL OUTPUT VO tPLH INPUT IF 1.5 V Figure 6. Test circuit for t PHL and t PLH. PWD - PULSE WIDTH DISTORTION - ns 150 tP - PROPAGATION DELAY - ns VCC = 3.3 V IF = 7.5 mA 50 VCC = 3.3 V IF = 7.5 mA 40 120 tPLH , R L = 350 90 30 RL = 350 60 tPHL , R L = 350 30 0 -60 -40 -20 20 10 0 20 40 60 80 100 0 -60 -40 -20 0 20 40 60 80 100 TA - TEMPERATURE - C TA - TEMPERATURE - C Figure 7. Typical propagation delay vs. temperature. Figure 8. Typical pulse width distortion vs. temperature. PULSE GEN. ZO = 50 tf = tr = 5 ns INPUT V E MONITORING NODE +3.3 V 1 VCC 8 7 6 *CL 4 GND 5 *CL IS APPROXIMATELY 15 pF WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE. 0.1 F BYPASS RL OUTPUT V O MONITORING NODE INPUT VE tEHL OUTPUT VO tELH 3.0 V 1.5 V 7.5 mA IF 2 3 1.5 V Figure 9. Test circuit for t EHL and tELH. IF SINGLE CHANNEL IF B A VFF 2 3 4 GND VCM - + PULSE GENERATOR ZO = 50 VCM VO 0V 3.3 V 7 6 5 1 VCC 8 0.1 F BYPASS RL OUTPUT V O MONITORING NODE VFF 3 4 GND VCM - + PULSE GENERATOR ZO = 50 6 5 0.1 F BYPASS +3.3 V B A 1 2 DUAL CHANNEL VCC 8 RL 7 +3.3 V OUTPUT V O MONITORING NODE VCM (PEAK) SWITCH AT A: I F = 0 mA VO (MIN.) SWITCH AT B: I F = 7.5 mA VO (MAX.) 0.5 V CML CMH VO Figure 10. Test circuit for common mode transient immunity and typical waveforms. GND BUS (BACK) VCC BUS (FRONT) NC ENABLE 0.1 F NC OUTPUT 10 mm MAX. (SEE NOTE 5) SINGLE CHANNEL DEVICE ILLUSTRATED. Figure 11. Recommended printed circuit board layout. SINGLE CHANNEL DEVICE VCC1 3.3 V 220 IF + D1* VF - 1 3 SHIELD VE 7 2 5 0.1 F BYPASS GND 2 2 6 8 RL 3.3 V VCC2 GND 1 *DIODE D1 (1N916 OR EQUIVALENT) IS NOT REQUIRED FOR UNITS WITH OPEN COLLECTOR OUTPUT. DUAL CHANNEL DEVICE CHANNEL 1 SHOWN VCC1 3.3 V 220 IF + D1* VF GND 1 1 - 2 SHIELD 2 5 0.1 F BYPASS GND 2 1 7 8 RL 3.3 V VCC2 Figure 12. Recommended LVTTL interface circuit. Application Information Common-Mode Rejection for HCPL-260L Families: Figure 13 shows the recommended drive circuit for optimal common-mode rejection performance. Two main points to note are: 1. The enable pin is tied to V CC rather than floating (this applies to single-channel parts only). 2. Two LED-current setting resistors are used instead of one. This is to balance ILED variation during commonmode transients. If the enable pin is left floating, it is possible for common-mode transients to couple to the enable pin, resulting in common-mode failure. This failure mechanism only occurs when the LED is on and the output is in the Low State. It is identified as occurring when the transient output voltage rises above 0.8 V. Therefore, the enable pin should be connected to either V CC or logic-level high for best common-mode performance with the output low (CMRL ). This failure mechanism is only present in single-channel parts which have the enable function. Also, common-mode transients can capacitively couple from the LED anode (or cathode) to the output-side ground causing current to be shunted away from the LED (which can be bad if the LED is on) or conversely cause current to be injected into the LED (bad if the LED is meant to be off). Figure 14 shows the parasitic capacitances which exists between LED anode/cathode and output ground (C LA and C LC). Also shown in Figure 14 on the input side is an AC-equivalent circuit. VCC 220 * 1 HCPL-260L 8 0.01 F 350 VCC+ 2 7 220 3 6 VO 74LS04 OR ANY TOTEM-POLE OUTPUT LOGIC GATE GND1 4 SHIELD 5 GND * GND2 * HIGHER CMR MAY BE OBTAINABLE BY CONNECTING PINS 1, 4 TO INPUT GROUND (GND1). Figure 13. Recommended drive circuit for High-CMR. 1 1/2 RLED 8 0.01 F VCC+ 350 2 ILP 1/2 RLED CLA 7 3 ILN 6 15 pF VO 4 CLC 5 SHIELD GND . + VCM - Figure 14. AC equivalent circuit. For transients occurring when the LED is on, common-mode rejection (CMR L, since the output is in the "low" state) depends upon the amount of LED current drive (I F). For conditions where IF is close to the switching threshold (ITH), CMRL also depends on the extent which ILP and ILN balance each other. In other words, any condition where common-mode transients cause a momentary decrease in I F will cause common-mode failure for transients which are fast enough. Likewise for common-mode transients which occur when the LED is off (i.e. CMR H, since the output is "high"), if an imbalance between ILP and ILN results in a transient IF equal to or greater than the switching threshold of the optocoupler, the transient "signal" may cause the output to spike below 2 V (which constitutes a CMRH failure). By using the recommended circuit in Figure 13, good CMR can be achieved. The balanced ILED -setting resistors help equalize ILP and ILN to reduce the amount by which ILED is modulated from transient coupling through C LA and CLC CMR with Other Drive Circuits CMR performance with drive circuits other than that shown in Figure 13 may be enhanced by following these guidelines: 1. Use of drive circuits where current is shunted from the LED in the LED off" state (as shown in Figures 15 and 16). This is beneficial for good CMRH . 2. Use of I FH > 3.5 mA. This is good for high CMRL. Figure 15 shows a circuit which can be used with any totem-poleoutput TTL/LSTTL/HCMOS logic gate. The buffer PNP transistor allows the circuit to be used with logic devices which have low current-sinking capability. It also helps maintain the driving-gate power-supply current at a constant level to minimize ground shifting for other devices connected to the input-supply ground. When using an open-collector TTL or open-drain CMOS logic gate, the circuit in Figure 16 may be used. When using a CMOS gate to drive the optocoupler, the circuit shown in Figure 17 may be used. The diode in parallel with the RLED speeds the turn-off of the optocoupler LED. " VCC HCPL-260L 420 (MAX) 2N3906 (ANY PNP) 1 2 LED 74L504 (ANY TTL/CMOS GATE) 3 4 Figure 15. TTL interface circuit. VCC R HCPL-260L 1 2 74HC00 (OR ANY OPEN-COLLECTOR/ OPEN-DRAIN LOGIC GATE) LED 3 4 Figure 16. TTL open-collector/open drain gate drive circuit. VCC 1N4148 HCPL-260L 1 2 74HC04 (OR ANY TOTEM-POLE OUTPUT LOGIC GATE) 220 LED 3 4 Figure 17. CMOS gate drive circuit. www.semiconductor.agilent.com Data subject to change. Copyright (c) 2000 Agilent Technologies 5980-2523EN (11/00) |
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